Field of the Invention
Generally, the present disclosure relates to the manufacture and use of sophisticated semiconductor devices, and, more specifically, to various methods, structures, and systems for improving the yield and/or reliability of semiconductor devices by exploitation of bias temperature instability (BTI).
Description of the Related Art
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. In this manner, integrated circuit chips may be fabricated.
Bias temperature instability (BTI) remains as one of the key reliability concerns in advanced complementary metal-oxide-semiconductor (CMOS) nodes, such as those used in static random access memory (SRAM). Generally, BTI arises when a voltage is applied to one or more transistors or other elements of a device incorporating CMOS technologies, i.e., during normal device operation. Over time, BTI tends to weaken the drive strength of the transistor. Of further concern in multi-element devices, such as, for example, six-transistor (6T) SRAMs, is that unequal extents of BTI between different elements may lead to imbalances between writability and read-stability (one cause of which is BTI shifts) that reduce yield of the circuit element more than would be expected from simply considering each BTI-undergoing element in isolation.
Field failures due to stress induced device shifts attributable to the BTI mechanism continue to plague very-large-scale integration (VLSI) CMOS technologies. Over product life time the Vmin is known to increase in large SRAM arrays due to negative bias temperature instability (NBTI) and more recently positive bias temperature instability (PBTI) combined with NBTI. SRAM arrays are particularly vulnerable due to the increased number of bits with each generation and use of minimum transistor size for maximum bit density.
The random nature of the BTI mechanism leaves large arrays vulnerable to BTI induced failures over the life time of the product. Therefore, BTI induced voltage sensitive failures in advanced VLSI SRAM arrays are expected to remain one of the key technology reliability concerns for the foreseeable future.
The industry has adopted voltage-guard-bands as the principle means to compensate for expected end of life BTI shifts. Though accepted, voltage-guard-bands are costly with limitations in effectiveness.
Therefore, it would be desirable to have solutions to the problem of BTI shifts that are relatively inexpensive, readily fabricated, and effective.
The present disclosure may address and/or at least reduce one or more of the problems identified above regarding the prior art and/or provide one or more of the desirable features listed above.